library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity regDest is
  
  port (
    sel    : in  std_logic_vector(1 downto 0);
    in1    : in  std_logic_vector(4 downto 0);
    in2    : in  std_logic_vector(4 downto 0);
    result : out std_logic_vector(4 downto 0));
end regDest;

architecture arch of regDest is

begin  -- arch

  with sel select
    result <=
    in1                                   when "10" ,
    in2                                   when "01",
    std_logic_vector(to_unsigned(31, 5)) when "00",
    std_logic_vector(to_unsigned(0, 5))  when others;

end arch;
